VLSI - Very Large Scale Integration MCQs
VLSI - Very Large Scale Integration MCQs
These VLSI - Very Large Scale Integration multiple-choice questions and their answers will help you strengthen your grip on the subject of VLSI - Very Large Scale Integration. You can prepare for an upcoming exam or job interview with these 70 VLSI - Very Large Scale Integration MCQs.
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1: An active current mirror means that ___________.
A. active devices are used as load
B. active devices are used as elements
C. it is always active in the circuit
D. None of these
2: Floating point data types provide an approximation of ___________.
A. complex numbers
B. rational numbers
C. even numbers
D. real numbers
3: For an npn Bipolar Transistor, gm ___________.
A. is dependent on input voltage
B. is dependent on IC
C. is independent of the process
D. All of these
4: Contacts between the metal layers are known as _____________.
A. contacts
B. cuts
C. vias
D. None of the above
5: How many Pass transistors can be connected in a series?
A. 3
B. 4
C. 5
D. 6
6: A signal data object in VHDL is an object with_______________.
A. a past history of values
B. a present history of values
C. a future history of values
D. a history without any values
7: For a given total bias current, the gain of a differential pair is________ more than the CS Stage.
A. 1/2
B. 1/4
C. 1/3
D. 1/√2
8: A fast CMOS circuit requires that the gm___________. (Where gm means transconductance).
A. should be small
B. should be high
C. should be independent of gm
D. should vary inversely with speed
9: High Electron Mobility Transistors(HEMT) are formed using alternating layers of _______________.
A. GaAs and silicon
B. GaAs and boron
C. GaAs and AlGaAs
D. GaAs and germanium GaAs
10: For the Orbit Process, the n-active and p-active regions have_________.
A. small capacitance
B. large capacitance
C. infinite capacitance
D. negligible capacitance
11: What is Metallization in IC Fabrication?
A. It is a process in which a layer of metal is deposited on a silicon wafer
B. It is a process in which a wafer is sliced by a metal
C. It is a process by which the components of an IC are inter connected by an aluminum conductor
D. It is a process in which a metal base is formed below the surface of a wafer
12: The separation between the Thinox Regions is of __________ .
A. 2λ
B. 3λ
C. 4λ
D. 5λ
13: If length (L) and width (W) are both scaled down by α, the area is scaled ___________. (Power Speed Product PT)
A. down by α
B. down by α2
C. up by α
D. None of these
14: What exactly is Behavioral Modeling in VHDL?
A. A set of concurrent statements
B. A set of interconnected components
C. A set of sequential program statements
D. A set of cumulative statements
15: Latch up introduces_________.
A. a low resistance path between adjacent devices
B. a low resistance path between the source and the drain
C. a low resistance path between the power supply and the ground
D. None of the above
16: What is Generic Array Logic(GAL) based on?
A. PROMs
B. EAROMs
C. EEPROMs
D. Flash Memory
17: The Double Metal MOS process is used to ____________.
A. increase the metal area
B. increase the VDD area
C. increase the VSS area
D. None of the above
18: In general, VDD and VSS are always distributed upon ____________.
A. Polysilicon layers
B. Metal Layers
C. Either of the above
D. None of these
19: MOS current sources are used to generate __________.
A. current Mirrors
B. current Steering Circuits
C. current Sink
D. All of these
20: Which execution platform is used for a behaviour-level VHDL?
A. Simulator
B. Operating system
C. Debugger
D. Real time operating system
21: The Cascode structure ___________.
A. has low output impedance
B. has high output impedance
C. is the product of output impedance of the two stages used
D. None of the above
22: Which one of the following statements is not correct about an entity in VHDL?
A. An entity is a description of the interface between a design and an external environment
B. An entity defines the input and output ports of a design
C. One entity has only one architecture
D. A design can contain more than one entity
23: Which one of the following is not a mode for ports in VHDL?
A. IN
B. OUT
C. Buffer
D. Tri-state
24: If length (L) and width (W) are both scaled down by α, the area is scaled down by __________.
A. α
B. α2
C. α/2
D. None of the above
25: In the Folded Cascode structure, ____________.
A. the current is folded up
B. the current is folded down
C. both of the above
D. none of the above
26: What does the Programmable Logic Array(PLA) consist of?
A. A programmable AND array and a programmable OR array
B. A programmable AND array and a fixed OR array
C. A fixed AND array and a programmable OR array
D. Fixed AND and OR arrays
27: What function does the scalar data type perform in VHDL?
A. It provides element values
B. It does not provide element values
C. It provides access to objects of a given type
D. It provides access to objects that contain a sequence of values
28: What is the function of the Alias statement?
A. It declares an alternate name for an existing named entity
B. It declares the same name again for an existing named entity
C. It declares a different name for a different entity
D. It declares the already used name for a different entity
29: Which of the following is the fastest technology in terms of propagation delay?
A. CMOS
B. ECL
C. BiCMOS
D. GaAs
30: When is the Boundary Scan Test (BST) used?
A. It is used to test the MOS function
B. It is used to test the fan-out of TTL family
C. It is used to test the output impedance of MOS
D. It is used to resolve problems associated with the testing of boards carrying VLSI circuits
31: Which one of the following is not a sequential statement in VHDL?
A. The Next statement
B. The Exit statement
C. The If statement
D. The Block statement
32: LSI and VLSI devices use_____________ technology.
A. TTL
B. ECL
C. MOS
D. CMOS
33: Which one of the following is a concurrent statement?
A. The main statement
B. The end statement
C. The process statement
D. The signal statement
34: Photolithography in IC Fabrication is___________.
A. the deposition of oxide in selective areas
B. the selective removal of oxide in the desired areas
C. a process for ion implantation
D. a process for annealing
35: In the BiCMOS process, the basic inverter is made by __________.
A. using mos as switch and BJT as driver
B. using mos as driver and BJT as switch
C. using either of the two as driver or switch
D. None of these
36: QHDL(Hardware Description Language) is used for _____________.
A. software design of circuits
B. hardware design of circuits
C. operating system design of circuits
D. real time operating system design of circuits
37: Under what condition does the Frenkel defect take place?
A. A vacancy in the lattice created due to a missing atom
B. A silicon atom in an interstitial lattice site with an associated vacancy
C. A non silicon atom in an interstitial lattice site with an associated vacancy
D. A vacancy in the lattice created due to a missing molecule
38: Which among the following conditions qualifies for a Latch-up in CMOS circuit condition?
A. When a high resistance path is established between the drain and the source
B. When a high resistance path is established between the drain and the gate
C. When a low resistance path is established between the drain and the source
D. When a low resistance path is established between the drain and the gate
39: If length (L) and width (W) are both scaled down by α, the area is scaled ___________. ron
A. down by α resistance
B. down by α2
C. up by α
D. None of these
40: Stick diagrams are used to __________.
A. convey the presence of Metal
B. Vconvey the presence of Gate
C. convey the presence of Contact
D. convey the layer information
41: Which kind of problem is eliminated by the NMOS superbuffers?
A. Symmetry of the conventional inverter
B. Low output problem of the conventional inverter
C. Asymmetry of the conventional inverter
D. High output problem of the conventional inverter
42: In the Cascode structure, the maximum voltage gain is roughly equal to ____________.
A. the sum of the intrinsic gain of the transistors
B. the product of the intrinsic gain of the transistors
C. the square of the intrinsic gain of the transistors
D. None of these
43: In VHDL, the prefix "V" stands for _____ .
A. VHSIC (very high switching integrated circuit)
B. VHSIC (very high speed integrated circuit)
C. VHSIC (very high speed integrated configuration)
D. VHSIC (verilog high switching integrated circuit)
44: What is the body effect on the input impedance of the Common Gate Configuration?
A. It decreases the input impedance
B. It increases the input impedance
C. The input impedance is independent of the body effect
D. None of these
45: Which of the following can act as a dopant for the formation of N-type gallium arsenide material?
A. Boron
B. Silicon
C. Germanium
D. Phosphorous
46: Which of the following parameters is advantageous in the case of BiCMOS technology?
A. Power dissipation
B. High o/p drive current
C. High noise margin
D. Low output drive current
47: The two metal layers are laid in a way that ______________.
A. the conductors are always parallel
B. the conductors are always orthogonal
C. the conductors are always touching
D. None of the above
48: In which condition is the Case statement used?
A. When the output of design depends on the value of one signal expression
B. When the behavior of design depends on the value of one signal expression
C. When the output of design depends on the value of two signal expression
D. When the behavior of design depends on the value of two signal expressions
49: Which kind of signal is converted into in the common source arrangement of the transistor?
A. Voltage signal
B. Current signal
C. Power signal
D. No idea
50: MOS in the Common Gate Configuration provides___________.
A. Inverted gain
B. Non inverted gain
C. Gain less than one
D. Unity gain
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